1. Field of the Invention
The present invention relates to a scanning line driving circuit, and more particularly to a shift register circuit applicable to a scanning line driving circuit for use as, e.g., an electro-optic apparatus such as an image display apparatus and an image sensor and constituted by only field-effect transistors of the same conductivity type.
2. Description of the Background Art
In an image display apparatus (hereinafter referred to as a “display apparatus”) such as a liquid crystal display apparatus, a plurality of pixels are arranged in a matrix on a display panel, and a gate line (scanning line) is provided for each row of pixels (pixel line) of the display panel. In a cycle of one horizontal period of a display signal, the gate lines are sequentially selected and driven to update a display image. As a gate line driving circuit (scanning line driving circuit) for sequentially selecting and driving pixel lines, i.e., gate lines, a shift register may be used, which performs a round of shift operation in one frame period of a display signal.
In order to reduce the number of steps in the manufacturing process of a display apparatus, a shift register for use as a gate line driving circuit should preferably be constituted by only field-effect transistors of the same conductivity type. Therefore, various types of shift registers constituted by only N- or P-type field-effect transistors, and various display apparatuses containing such shift registers have been proposed (e.g., in Japanese Patent Application Laid-open No. 2004-78172).
A shift register for use as a gate line driving circuit is constituted by a plurality of cascade-connected shift register circuits, each of which is provided for each pixel line, i.e., each gate line. In this specification, for convenience of description, each of a plurality of shift register circuits forming a gate line driving circuit is referred to as a “unit shift register.” In other words, an output terminal of each unit shift register constituting a gate line driving circuit is connected to an input terminal of a unit shift register of a subsequent stage or a later stage.
FIG. 7 of Japanese Patent Application Laid-open No. 2004-78172 illustrates a configuration of a conventional unit shift register. As shown in FIG. 7 thereof, the conventional unit shift register includes a first transistor (M1) connected between an output terminal of an output signal (GOUT[N]) and a clock terminal provided with a clock signal (CKV) and a second transistor (M2) connected between the output terminal and a first power supply terminal (VOFF). The unit shift register outputs the output signal (GOUT[N]), when the clock signal (CKV) is transmitted to the output terminal through the first transistor (M1) while the first transistor (M1) is on and the second transistor (M2) is off.
In particular, it is necessary for a gate line driving circuit to activate a gate line by charging it rapidly using the output signal, and accordingly, in each unit shift register constituting the gate line driving circuit, the first transistor (M1) is required to have a high drive capability (a capability to pass current). Therefore, a gate width (channel width) of the first transistor (M1) is configured to be wide.
A first node (N1), to which the gate of the first transistor (M1) is connected, is connected to a third transistor (M4) for discharging the first node (N1) in a period in which the output signal (GOUT[N]) is a non-active level (non-selection period). The third transistor (M4) is connected between the first node (N1) and the first power supply terminal (VOFF). The unit shift register has an inverter (M6, M7) whose input end is the first node (N1), and the gate of the third transistor (M4) is connected to a second node (N2), i.e., an output end of the inverter.
The unit shift register is configured to maintain the second node (N2) at the H level in the non-selection period. Therefore, in the non-selection period, the third transistor (M4) is in the on-state, and the first node (N1) is maintained at the L level in a low impedance. Accordingly, the first transistor (M1) is maintained in the off-state. Since the second transistor (M2) is turned into the on-state, the output terminal (GOUT[N]) is fixed to the L level.
In a generally-used gate-insulated field-effect transistor, a drain (source) electrode and a gate electrode are arranged to overlap with each other in a certain area so as to allow connection between the drain electrode and the source electrode via a conductive channel. Therefore, there is a capacitive component called an overlap capacitance between the drain and the gate (source). Especially, thin film transistors using amorphous silicon tend to have a large overlap capacitance, which, in some cases, amounts to about the same as a capacitance between the gate and the channel.
In the above unit shift register, in the non-selection period, the first transistor (M1) is in the off-state, but the clock signal (CKV) is continuously provided to the drain thereof (clock terminal). Therefore, when the clock signal (CKV) rises (changes from the L level to the H level), the potential at the first node (N1) increases due to the coupling via the overlap capacitance. Since the third transistor (M4) is turned off at this moment, the first node (N1) instantly gets back to the L level, and the first transistor (M1) is maintained in the off-state, which prevents the unit shift register from malfunctioning.
However, a current (capacitive coupling current) flows from this clock terminal to the first power supply terminal (VOFF) through the overlap capacitance of the transistor Q1, the first node (N1), and the third transistor (M4). This current is not so much large in one unit shift register, but the gate line driving circuit has many unit shift registers to which the same clock signal is provided. Therefore, the current is considered to be rather large in terms of the gate line driving circuit.
In other words, the capacitive coupling current increases in proportional to the number of stages of shift registers, i.e., the number of gate lines, in the gate line driving circuit. Therefore, when a display apparatus has a large display area with many lines of pixels, a correspondingly large capacitive coupling current flows. As a result, there arises a problem in that a power consumption places a restriction on enlargement of a display area (achieving a large screen).
In the unit shift register of FIG. 7 of Japanese Patent Application Laid-Open No. 2004-78172, this problem may be solved by a method of reducing the overlap capacitance by reducing the gate width of the first transistor (M1). However, as described above, the first transistor (M1) is required to have a high driving capacity, and therefore, it is not preferable to narrow the gate width.